On 10/18/2016 12:32 PM, Tero Kristo wrote:
On 18/10/16 18:56, Matthijs van Duin wrote:
On 18 October 2016 at 17:10, Tero Kristo <t-kristo@xxxxxx> wrote:
Based on some internal discussions, and the fact that the data manual for
DRA7 doesn't mention this feature (even though it is listed in TRM) my
current assumption is that it is not needed on that SoC.
Do you have any insights w.r.t. the first part of my email? Is there
any hope of finding out what the actual max speed is of the async
bridge, and what the consequences might be of exceeding it?
Personally I don't have any idea. It may impact the lifetime of the SoC,
thats my best guess. I think Nishanth tried to ask around a bit about
this, but if that didn't result into any reasonable answers, the best
approach would be to raise a question in the TI support forums.
Nishanth, any thoughts?
I have'nt had luck via the internal channels I know of - yes, I do
suggest e2e.ti.com as the best option. Though [1] seems to have gone
read-only ; however, reading [2], best I can find is [3].
[1] http://e2e.ti.com/support/omap/f/885
[2] http://www.ti.com/product/OMAP5432/support#community
[3] http://e2e.ti.com/support/dsp/omap_applications_processors
--
Regards,
Nishanth Menon
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