On 18/10/16 18:56, Matthijs van Duin wrote:
On 18 October 2016 at 17:10, Tero Kristo <t-kristo@xxxxxx> wrote:
Based on some internal discussions, and the fact that the data manual for
DRA7 doesn't mention this feature (even though it is listed in TRM) my
current assumption is that it is not needed on that SoC.
Do you have any insights w.r.t. the first part of my email? Is there
any hope of finding out what the actual max speed is of the async
bridge, and what the consequences might be of exceeding it?
Personally I don't have any idea. It may impact the lifetime of the SoC,
thats my best guess. I think Nishanth tried to ask around a bit about
this, but if that didn't result into any reasonable answers, the best
approach would be to raise a question in the TI support forums.
Nishanth, any thoughts?
-Tero
As I said, currently that bridge is being severely overclocked on any
omap5 running a mainline kernel at OPP_HIGH, yet no problems are
apparent even if I flood the L3 bridge with traffic. Setting the
divider to /8 on the other hand hurts MPU-L3 performance badly and
L3-heavy use cases may want to avoid it, leaving the choice of either
sacrificing cpu speed or just keeping things as it is now and hope for
the best.
Matthijs
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
