On 18 November 2015 at 09:26, Delio Brignoli <dbrignoli@xxxxxxxxxxxxxxxx> wrote: >> This works in principle, but both minimizing the DCO and (often >> needlessly) using the fractional multiplier seem like recipes to >> maximize the clock jitter. Mind you, I don't know how much jitter >> we’re talking about here, I don't recall having seen specs about this. > > We haven’t seen any specs either but testing shows that changing DCO mode causes > the PLL to lose lock at least temporarily. Losing lock on reconfiguration is entirely a separate matter from clock jitter. The fractional multiplier works by essentially by alternating between the nearest integer multiplier values. This will be smoothed out by the loop filter, but it's not going to vanish. To put this in perspective, some docs (I can't immediately find which one) warned that when using the fractional multiplier of DPLLS, its value needed to be at least 100 to ensure max 2.5% jitter. To put this in perspective, if I grab the datasheet of an audio DAC I find: Although the architecture of the PCM4104 is tolerant to phase jitter on the system clock, it is recommended that the user provide a low jitter clock (100 picoseconds or less) for optimal performance. For a typical 24.576 MHz audio system clock that means max 0.25% jitter. Whoops :P Now DPLLLJ will presumably do better, but without actual specs the safe option is to avoid the fractional multiplier altogether. Matthijs -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
