On 18 Nov 2015, at 06:22, Matthijs van Duin <matthijsvanduin@xxxxxxxxx> wrote: > The PLL code looks pretty mediocre to me. In particular, they make no > effort whatsoever to configure an exact ratio. It seems their > algorithm uses whatever pre divider was already programmed, I believe the implementors assumed the bootloader was setting up the PLL, its adjustment may have been an afterthought added in order to support PTP. > This works in principle, but both minimizing the DCO and (often > needlessly) using the fractional multiplier seem like recipes to > maximize the clock jitter. Mind you, I don't know how much jitter > we’re talking about here, I don't recall having seen specs about this. We haven’t seen any specs either but testing shows that changing DCO mode causes the PLL to lose lock at least temporarily. — Delio -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
