On 10 April 2015 at 00:37, Grazvydas Ignotas <notasas@xxxxxxxxx> wrote: > May I ask how do you perform the smc call? A point worth mentioning is that TI advises that r1-r4 may be clobbered in general, and at least on GP dm814x and am335x devices r4 is in fact clobbered, even though it is normally a callee-save register. Also, on aforementioned devices, the secure-world MMU is enabled, with translation table 0 being 1KB @ 0x402f2000, used for secure VA 0x00000000 - 0x0fffffff (the rest goes via translation table 1 in secure ROM). It is generally not consulted in practice since secrom locks two dTLB and two iTLB entries. The GP secure monitor doesn't actually perform any data access whatsoever, so the two dTLB can and should be unlocked considering that TLB entries are a rather scarce resource (32 per side) and a dTLB miss incurs a 24-cycle minimum penalty (compare with 8-cycle minimum penalty for L1 cache miss). Unlocking the second iTLB entry is also safe, but if both iTLB entries are unlocked, you need to preserve or repopulate the relevant translation entry (VA 0x00300000 -> PA 0x00000000) to be able to perform an SMC. Everything that happens in secure monitor mode is heavily double-checked by the SSM, so while you're free to choose a cache policy, any creativity beyond that will piss off the SSM and cause it to hit the "MPU security violation" global reset. Once appropriate fixes to the auxiliary control register have been applied, generally no further SMCs are needed hence all TLB entries can be unlocked. Since it would be reasonable for a bootloader to do this, I recommend checking whether a fix is needed and not unconditionally performing an SMC. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
