On 5.04.2015 19:50, Matthijs van Duin wrote:
On 5 April 2015 at 09:23, Ivaylo Dimitrov <ivo.g.dimitrov.75@xxxxxxxxx> wrote:
Though I wonder why SMC is needed to write ACR on non-HS devices. A simple
MRC should suffice, unless I miss something.
Public-world access to ACR varies per bit:
bit 1 (L2EN) is documented as banked, but at least on r3p2 turns out
to be common r/w.
bits 30-31 are secure read-only and public RAZ.
remaining bits are secure read/write and public read-only.
The net effect is that doing an MRC from public world will only modify
the L2EN bit.
There's no bit in the non-secure access control register to affect all
of this, so GP vs HS doesn't matter here (from a CPU point of view; it
may matter for the availability of SM calls obviously).
Matthijs
But then the first part(setting the IBE bit in ACR to 1) of the errata
workaround is wrong, as it uses a plain MCR to set the IBE bit, see
http://lxr.free-electrons.com/source/arch/arm/mm/proc-v7.S#L340. Which
is weird, given that the workaround was posted by ARM iirc.
Ivo
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