* Sebastian Andrzej Siewior | 2014-09-24 09:53:46 [+0200]:
>* Peter Hurley | 2014-09-23 13:03:51 [-0400]:
>
>>But DMA is cheating if the UART driver's tx_empty() method is saying the
>>transmitter is empty while TX DMA is still running.
>This shouldn't be the case. But I will check this once I able to.
I added
|#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
| trace_printk("delay <%d>\n", (lsr & BOTH_EMPTY) == BOTH_EMPTY ? 1 : 0);
in my set_termios() and the trace shows
| vi-949 [000] d... 70.477002: omap8250_restore_regs: delay <0>
so no, it does not wait until TX FIFO is empty. It looks like it uses
TCSANOW instead of TCSADRAIN. And since this looks "legal" I will delay
it until TX-DMA is complete because it is known to stall the DMA operation.
>>Regards,
>>Peter Hurley
Sebastian
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