On Fri, 2009-02-20 at 21:59 +0100, ext Woodruff, Richard wrote: > > I received the following comment from a HW Apps person whom has dealt with this at the board level. > > <comment start> > Attached is the I2C spec that I have. As I understand it, the I2C only specify the minimum tLow and tHigh (which is not "balanced"). However what is more important is that the appropriate setup and hold time are followed. > > If the equal time still meets the setup/hold time then there should not be any issue from a compliance standpoint. > <comment end> > > Regards, > Richard W. Hi, With out board, the tLow and tHigh values are in line with I2C standard with the patch: http://marc.info/?l=linux-omap&m=122770723311340&w=2 Would that risk the setup and hold times? (If I remember correctly, the values (setup, hold) were within the I2C standard even with the patch.) I think it's a risk not to meet tLow and tHigh. I'm saying, with open source values with our board, the tLow was not in standard. If using TRM minimum values, things get even worse. Why? because it states, for example, Fast Mode SCLL = 5 and SCLH = 7. This means that the low period is smaller than the high! Shouldn't it be vice versa? (scope verified). - Eero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
