Re: [PATCH v4 3/6] ARM: dts: dra7: add support for parallel NAND flash

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Hi Pekon,

On 05/12/2014 12:05 PM, Gupta, Pekon wrote:
>> From: Javier Martinez Canillas [mailto:javier@xxxxxxxxxxxx]
> [...]
> 
>>> Newer platforms have upgraded version of GPMC engine which supports
>>> BCH16 ECC scheme in hardware. Thus the GPMC address space was
>>> expanded to include some extra registers required for BCH16 ECC [2].
>>>
>>>
>>
>> I see and did the GPMC register space became that big to need to map 8KB?
>>
>> Although the smallest unit for ioremap is PAGE_SIZE and using any of
>> these reg sizes:
>>
>> reg = <0x6e000000 0x02d0>;
>> reg = <0x6e000000 0x0400>;
>> reg = <0x6e000000 0x1000>;
>>
>> in practice have the same effect, DTS should describe the hardware and
>> not an implementation detail so I think that we should use only the
>> register size that is defined in the TRM.
>>
> Yes, I agree with you.
> I have fixed this in newer version of the patch and will be sending it soon.
> But this series will only contain updates for new platforms with addition
> of NAND node in DTS, so that this series is not stalled for any reason.
> For fixing existing platform/boards DTS I'll send another series soon.
> 
> For now, I'll use GPMC address-space size = 0x380 as it matches with
> actual hardware and is working.

How did you get 0x380?

>From DRA7 TRM, GPMC address range is 0x5000 0000 : 0x5000 02D0
So the address-space size should be 0x2D4 (as last register@2D0 is 32-bits wide)

For the ELM module it should be 4KB i.e. 0x1000

cheers,
-roger

>>>
>>> [1] http://www.ti.com/lit/gpn/am3359    (Section 7.4 to 7.4.5)
>>>
>>> [2] http://www.ti.com/lit/gpn/am3359    (Section 7.1 to 7.1.5)
>>> (Though the AM335x address space mentions 0x368 as last address,
>>>  it should be 0x378. I have raised documentation bug for it).
>>>
>>>
>>> with regards, pekon
>>
>> Best regards,
>> Javier
>>
>> [0]: http://lxr.free-electrons.com/source/arch/arm/mm/ioremap.c#L334
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