1) NAND device memory is not directly accessible to CPU, its indirectly accessed
via registers. So the 'reg' property for GPMC NAND nodes should be limited to
address range of internal GPMC registers only.
2) Also, minimum granularity of address space under a GPMC chip-select is 16MB
so 'range' property for GPMC NAND node should specify 16MB as its memory-size
3) On AM437x, address map of external memory accessible via GPMC starts from 0x0
Signed-off-by: Pekon Gupta <pekon@xxxxxx>
---
arch/arm/boot/dts/am335x-evm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 33f7c57..bae7575 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -437,9 +437,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins_s0>;
- ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
+ ranges = <0 0 0 0x1000000>; /* CS0: NAND */
nand@0,0 {
- reg = <0 0 0>; /* CS0, offset 0 */
+ reg = <0 0 0x380>; /* CS0, offset=0, reg-map size=0x380 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
--
1.8.5.1.163.gd7aced9
--
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