On Wednesday 17 December 2008, Kanigeri, Hari wrote: > When the DSP processes data, the DSP cache controller > loads 128-Byte chunks (lines) from SDRAM and writes the > data back in 128-Byte chunks. In short: it's the same kind of cache line sharing issue that any other DMA-using software needs to be aware of, except that (a) the lines are 128 bytes vs whatever ARM uses, and (b) the other bus master is a CPU instead of something relatively dumb. Any software that runs on non-x86 hardware will likely have had to deal with such issues already, since most hardware other than x86 relies on software to prevent cache coherency goofs: no bus snooping, MOESI, etc. - Dave > If a DMM buffer does not start and end on a 128-Byte > boundary, the data preceding the start address from > the 128-Byte boundary to the Start Address and the > data at addresses trailing the end address from the > End Address to the next 128-Byte boundary will be > loaded and written back as well. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
