Kevin Hilman wrote:
Paul Walmsley wrote:
Commit 8b1f0bd44fe490ec631230c8c040753a2bda8caa introduced a bug that
caused non-CORE DPLL rates to be incorrectly set on boot in
omap3_noncore_dpll_enable(). Debugged by Tomi Valkeinen
<tomi.valkeinen@xxxxxxxxx> - thanks Tomi.
Also fix omap3_noncore_dpll_set_rate() to assign clk->rate after a
DPLL reprogram.
Tested on 3430SDP.
FYI, This patch breaks the ability to come out of retention in dynamic
idle, but I haven't yet discovered why.
It appears this is related to the UART patches being used in the PM
branch, and not this patch.
I have a (forthcoming) set of UART updates that will allow the UART to
disable its clocks and enable the chip to hit retention.
Kevin
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