* Nathan Monson <nmonson@xxxxxxxxx> [081016 07:52]: > On Wed, Oct 15, 2008 at 4:57 AM, Paul Walmsley <paul@xxxxxxxxx> wrote: > > Hi Nathan, > > > > could you try Lauri's patch posted here: > > http://marc.info/?l=linux-omap&m=122407150608770&w=2 > > without the strongly-ordered memory patches? > > This patch works for my DSP test case. > > I receive 10-20 kernel messages per second as follows: > irq -33, desc: c0414580, depth: 0, count: 0, unhandled: 0 > > However, DSP Bridge continues to function normally without errors. Here's my patch to attempt to fix this issue, could you all give it a try please? So far it has worked for me, I'd like to hear what Nathan's dsp test case does! Basically it's modified patch from Russell, except reading back the revision register is not enough. Looks like we need to read back the same register we're writing. I guess the L3/L4 is finer grained than ARM memory attributes? Regards, Tony
>From e708817b51069acf8a9bce20713243741981bd43 Mon Sep 17 00:00:00 2001 From: Tony Lindgren <tony@xxxxxxxxxxx> Date: Thu, 16 Oct 2008 10:52:51 -0700 Subject: [PATCH] ARM: OMAP: Read back the interrupt registers after write to ensure posting On 34xx interrupts would occasionally get stuck in spurious interrupt loop. Spurious interrupts are triggered on 34xx if the interrupt mask or priority registers are changed while the interrupt is asserted, see "10.5.4 MPU INTC Spurious Interrupt Handling" in the 34xx TRM. TI's suggestion was to map L3 and L4 as strongly ordered, while Russell's suggestion was to read back the revision register to ensure posting: http://www.mail-archive.com/linux-omap@xxxxxxxxxxxxxxx/msg02904.html However, looks like reading back INTC_REVISION is not enough with L3 and L4 busses. We need to read back the same register as we're writing to ensure it gets posted. See also "7.3 Memory attributes" in Cortex-A8 TRM. Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx> diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 4ffb4f1..facf886 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -64,6 +64,7 @@ static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) static void omap_ack_irq(unsigned int irq) { intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL); + intc_bank_read_reg(&irq_banks[0], INTC_CONTROL); } static void omap_mask_irq(unsigned int irq) @@ -73,6 +74,7 @@ static void omap_mask_irq(unsigned int irq) irq &= (IRQ_BITS_PER_REG - 1); intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset); + intc_bank_read_reg(&irq_banks[0], INTC_MIR_SET0 + offset); } static void omap_unmask_irq(unsigned int irq)
