RE: [PATCH] Added sleep support to UART

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Hi Tero,

Let me begin by saying that I don't care too much about the 32-bit SCM 
register read change; I just happen to think that it is easier to read.  
That said, one comment of yours bears some additional discussion:

On Thu, 12 Jun 2008, Tero.Kristo@xxxxxxxxx wrote:

> Also, the spec says that these registers can be accessed in either 8, 16
> or 32 bit modes so why make it unnecessarily complicated and potentially
> buggy with shifts (race conditions)?

What race are you referring to?  Wouldn't such a race exist with the 
current code?  (i.e., a shift should not cause any further race)


- Paul
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