Re: NIC with msg signaled interrupts on a SMP machine

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Stephen Hemminger wrote:
>> My kernel has SMP and Message-Signaled Interrupts (MSI) enabled. When I
>> boot with MSI enabled, I can see in /proc/interrupts that each of the
>> NICs got a unique interrupt assigned. But all traffic generated to the
>> 1st NIC goes to the CPU#0, other CPUs show 0 processed interrupts in the
>> /proc/interrupts.
> 
> This is actually a designed beneficial state. If IRQ's happen on different
> CPU's then there is more cache memory thrashing and performance is lower.
> 
OK, that's a good explanation. Now assuming the designed CPU processes
the incoming IRQ and puts (e.g.) incoming packet/skb into a queue.

I read once in the past, that these queues are per-CPU (to avoid
locking), so the same CPU has to process the packet doing iptables stuff
etc. Is that true ?

-Svata

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