Hi Boris,
On 29/4/2020 10:22 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar, Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> wrote:
+
+#define EBU_ADDR_SEL(n) (0x20 + (n) * 4)
+#define EBU_ADDR_MASK (5 << 4)
It's still unclear what ADDR_MASK is for. Can you add a comment
explaining what it does?
Thank you Boris, keep review and giving inputs, will update.
+#define EBU_ADDR_SEL_REGEN 0x1
+
+ writel(lower_32_bits(ebu_host->cs[ebu_host->cs_num].nand_pa) |
+ EBU_ADDR_SEL_REGEN | EBU_ADDR_MASK,
+ ebu_host->ebu + EBU_ADDR_SEL(reg));
+
+ writel(EBU_MEM_BASE_CS_0 | EBU_ADDR_MASK | EBU_ADDR_SEL_REGEN,
+ ebu_host->ebu + EBU_ADDR_SEL(0));
+ writel(EBU_MEM_BASE_CS_1 | EBU_ADDR_MASK | EBU_ADDR_SEL_REGEN,
+ ebu_host->ebu + EBU_ADDR_SEL(reg));
That's super weird. You seem to set EBU_ADDR_SEL(reg) twice. Are you
sure that's needed, and are we setting EBU_ADDR_SEL(0) here?
You are right, its weird only, but we need it, since different chip
select has different memory region access address.
Yes , we are setting both CS0 and CS1 memory access region, if you have
any concern to optimize, please suggest me, Thanks!
Regards
Vadivel
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