On Mon, Jan 28, 2019 at 10:27:39AM +0100, Miquel Raynal wrote: Hi Miquel, > Hi Naga, > > Naga Sureshkumar Relli <nagasure@xxxxxxxxxx> wrote on Mon, 28 Jan 2019 > 06:04:53 +0000: > > > Hi Boris & Miquel, > > > > Could you please provide your thoughts on this driver to support HW-ECC? > > As I said previously, there is no way to detect errors beyond N bit. > > I am ok to update the driver based on your inputs. > > We won't support the ECC engine. It simply cannot be used reliably. > > I am working on a generic ECC engine object. It's gonna take a few > months until it gets merged but after that you could update the > controller driver to drop any ECC-related function. Although the ECC Could you please let me know that, when can we expect generic ECC engine update in mtd NAND? Based on that, i will plan to update the ARASAN NAND driver along with your comments mentioned above under this update, as you know there is a limiation in ARASAN NAND controller to detect ECC errors. i am following this series https://patchwork.kernel.org/patch/10838705/ Thanks, Naga Sureshkumar Relli > engine part is blocking, raw access still look wrong and the driver > still needs changes. > > > Thanks, > Miquèl > > ______________________________________________________ > Linux MTD discussion mailing list > http://lists.infradead.org/mailman/listinfo/linux-mtd/ ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/