On 19/10/2022 13:06, Dinh Nguyen wrote: Thank you for your patch. There is something to discuss/improve. > -allOf: > - - $ref: "synopsys-dw-mshc-common.yaml#" > - > maintainers: > - Ulf Hansson <ulf.hansson@xxxxxxxxxx> > > @@ -38,6 +35,35 @@ properties: > - const: biu > - const: ciu > > + altr,sysmgr-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to the sysmgr node > + - description: register offset that controls the SDMMC clock phase > + - description: register shift for the smplsel(drive in) setting > + description: > + Contains the phandle to System Manager block that contains > + the SDMMC clock-phase control register. The first value is the pointer > + to the sysmgr, the 2nd value is the register offset for the SDMMC > + clock phase register, and the 3rd value is the bit shift for the > + smplsel(drive in) setting. > + > +allOf: > + - $ref: "synopsys-dw-mshc-common.yaml#" If there is going to be resend, please drop quotes here. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
