Re: [PATCH] mmc: sdhci-pci: Prefer SDR25 timing for High Speed mode for BYT-based Intel controllers

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On 11/11/20 7:34 am, Adrian Hunter wrote:
> On 10/11/20 2:01 pm, Ulf Hansson wrote:
>> On Fri, 6 Nov 2020 at 14:48, Adrian Hunter <adrian.hunter@xxxxxxxxx> wrote:
>>>
>>> A UHS setting of SDR25 can give better results for High Speed mode.
>>>
>>> Signed-off-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
>>> Cc: stable@xxxxxxxxxxxxxxx # v5.4+
>>> ---
>>>  drivers/mmc/host/sdhci-pci-core.c | 13 +++++++++++--
>>>  1 file changed, 11 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
>>> index 23da7f7fe093..9552708846ca 100644
>>> --- a/drivers/mmc/host/sdhci-pci-core.c
>>> +++ b/drivers/mmc/host/sdhci-pci-core.c
>>> @@ -665,6 +665,15 @@ static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
>>>         }
>>>  }
>>>
>>> +static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host,
>>> +                                         unsigned int timing)
>>> +{
>>> +       /* Set UHS timing to SDR25 for High Speed mode */
>>> +       if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS)
>>> +               timing = MMC_TIMING_UHS_SDR25;
>>
>> I don't quite get this. If the mmc core requests high speed mode, you
>> override this with timing settings corresponding to UHS_SDR25, right?
> 
> Yes.  There is no setting corresponding to high speed.  Currently SDHCI sets
> no value, which means zero which is also the setting for SDR12.  There was
> an attempt to change this in sdhci.c but it caused problems for some
> drivers, so it was reverted and the change was made to sdhci-brcmstb in
> commit 2fefc7c5f7d16e ("mmc: sdhci-brcmstb: Fix incorrect switch to HS
> mode").  Several other drivers also do this.
> 

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