On Fri, 6 Nov 2020 at 14:48, Adrian Hunter <adrian.hunter@xxxxxxxxx> wrote:
>
> A UHS setting of SDR25 can give better results for High Speed mode.
>
> Signed-off-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx # v5.4+
> ---
> drivers/mmc/host/sdhci-pci-core.c | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
> index 23da7f7fe093..9552708846ca 100644
> --- a/drivers/mmc/host/sdhci-pci-core.c
> +++ b/drivers/mmc/host/sdhci-pci-core.c
> @@ -665,6 +665,15 @@ static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
> }
> }
>
> +static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host,
> + unsigned int timing)
> +{
> + /* Set UHS timing to SDR25 for High Speed mode */
> + if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS)
> + timing = MMC_TIMING_UHS_SDR25;
I don't quite get this. If the mmc core requests high speed mode, you
override this with timing settings corresponding to UHS_SDR25, right?
> + sdhci_set_uhs_signaling(host, timing);
> +}
> +
> #define INTEL_HS400_ES_REG 0x78
> #define INTEL_HS400_ES_BIT BIT(0)
>
> @@ -721,7 +730,7 @@ static const struct sdhci_ops sdhci_intel_byt_ops = {
> .enable_dma = sdhci_pci_enable_dma,
> .set_bus_width = sdhci_set_bus_width,
> .reset = sdhci_reset,
> - .set_uhs_signaling = sdhci_set_uhs_signaling,
> + .set_uhs_signaling = sdhci_intel_set_uhs_signaling,
> .hw_reset = sdhci_pci_hw_reset,
> };
>
> @@ -731,7 +740,7 @@ static const struct sdhci_ops sdhci_intel_glk_ops = {
> .enable_dma = sdhci_pci_enable_dma,
> .set_bus_width = sdhci_set_bus_width,
> .reset = sdhci_cqhci_reset,
> - .set_uhs_signaling = sdhci_set_uhs_signaling,
> + .set_uhs_signaling = sdhci_intel_set_uhs_signaling,
> .hw_reset = sdhci_pci_hw_reset,
> .irq = sdhci_cqhci_irq,
> };
> --
> 2.17.1
>
Kind regards
Uffe
