Hi Philip
<snip>
> >
> > I catched a slight difference between the mainline and vendor driver
> > in DDR mode.
> >
> > the phase is set to 1
> > case MMC_TIMING_UHS_DDR50:
> > case MMC_TIMING_MMC_DDR52:
> > dat_drv_ph = 1;
> > speed_mod = SM2_HSDDR52_DDR50;
> > break;
> >
> > Could you add a hack in DDR mode and see if it's working better ?
> >
> > Maybe line 738:
> >
> > #define SDXC_REG_DRV_DL (0x0140)
> > #define SDXC_DAT_DRV_PH_SEL BIT(17)
> >
> > rval = mmc_readl(host, REG_DRV_DL);
> > rval |= SDXC_DAT_DRV_PH_SEL;
> > mmc_writel(host, REG_DRV_DL, rval);
>
> I tried with this patch but no luck, see log below
>
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -230,6 +230,8 @@
>
> #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/
>
> +#define SDXC_DAT_DRV_PH_SEL BIT(17)
> +
> struct sunxi_mmc_clk_delay {
> u32 output;
> u32 sample;
> @@ -718,6 +720,7 @@
> struct mmc_ios *ios, u32 rate)
> {
> int index;
> + u32 rval;
>
> /* clk controller delays not used under new timings mode */
> if (host->use_new_timings)
> @@ -736,6 +739,10 @@
> if (ios->timing != MMC_TIMING_UHS_DDR50 &&
> ios->timing != MMC_TIMING_MMC_DDR52) {
> index = SDXC_CLK_50M;
> +
> + rval = mmc_readl(host, REG_DRV_DL);
> + rval |= SDXC_DAT_DRV_PH_SEL;
> + mmc_writel(host, REG_DRV_DL, rval);
> } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
> index = SDXC_CLK_50M_DDR_8BIT;
> } else {
Sorry this will not work, as H6 uses new timing mode the function will
return before setting the DRV_PHASE.
Could you retry with a patch like this :
https://github.com/clementperon/linux/commit/287a62a6e9ccda3ade9b407ce12ee7db0865b41b.patch
Thanks for your test,
Clement
<snip>
>
> Regards,
> Philip
>
> > Regards,
> > Clement
> >
> >>
> >> Regards,
> >> Clement
> >>
> >>>
> >>> Maxime
>
