Hi, the Olimex A64-OLinuXino board comes in various variants, three with eMMC. While MMC HS-DDR mode works fine on one of them (A64-OLinuXino-1Ge4GW) it doesn't work on the A64-OLinuXino-2Ge8G-IND variant (I don't have the third variant so I can't check if it works there). Disabling MMC HS-DDR mode fixes the problem. This is also what Olimex does for their kernel: https://github.com/OLIMEX/linux-olimex/commit/eef0e814e74f.patch Mainline kernel doesn't differentiate between the different variants with eMMC so I'm disabling HS-DDR mode for all of them as done for the H5 eMMC controller. Disable HS-DDR mode for Olimex A64-OLinuXino variants with eMMC Signed-off-by: Philip Rinn <rinni@xxxxxxxxxxxxx> --- drivers/mmc/host/sunxi-mmc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index fc62773602ec..240d3803b8b9 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -1397,7 +1397,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev) MMC_CAP_SDIO_IRQ; /* - * Some H5 devices do not have signal traces precise enough to + * Some devices do not have signal traces precise enough to * use HS DDR mode for their eMMC chips. * * We still enable HS DDR modes for all the other controller @@ -1405,7 +1405,8 @@ static int sunxi_mmc_probe(struct platform_device *pdev) */ if ((host->cfg->clk_delays || host->use_new_timings) && !of_device_is_compatible(pdev->dev.of_node, - "allwinner,sun50i-h5-emmc")) + "allwinner,sun50i-h5-emmc") && + !of_machine_is_compatible("olimex,a64-olinuxino-emmc")) mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; ret = mmc_of_parse(mmc); -- 2.28.0
Attachment:
signature.asc
Description: OpenPGP digital signature
