On Thu, Jan 11, 2018 at 11:11 PM, Benoît Thébaudeau
<benoit.thebaudeau.dev@xxxxxxxxx> wrote:
> Dear Wladimir J. van der Laan,
>
> On Thu, Jan 11, 2018 at 6:15 PM, Wladimir J. van der Laan
> <laanwj@xxxxxxxxx> wrote:
>> Hello,
>>
>> I'm experiencing issues with kernel 4.15.0-rc5 on a MX53 LOCO board.
>>
>> Setup is two 32GB Samsung microSD SDHC cards plugged in
>>
>> mmc0 plugged indirectly: contains boot and auxiliary data
>> mmc1 through SD->microSD adapter that came with the card: contains root fs
>>
>> Initial error is "mmcblk1: error -84 transferring data, sector 2048, nr 8, cmd
>> response 0x900, card status 0xc00". Then various SDHCI REGISTER DUMP follow
>> after timeouts and CRC errors. It looks like the filesystem is corrupting,
>> resulting in a failed boot.
>>
>> Bisection gives me:
>>
>> 5143c953a7864c7abacf1c167c4350d641626949 is the first bad commit
>> commit 5143c953a7864c7abacf1c167c4350d641626949
>> Author: Benoît Thébaudeau <benoit@xxxxxxxxxxx>
>> Date: Tue May 30 11:14:10 2017 +0200
>>
>> mmc: sdhci-esdhc-imx: Allow all supported prescaler values
>>
>> On i.MX, SYSCTL.SDCLKFS may always be set to 0 in order to make the SD
>> clock frequency prescaler divide by 1 in SDR mode, even with the eSDHC.
>> The previous minimum prescaler value of 2 in SDR mode with the eSDHC was
>> a code remnant from PowerPC, which actually has this limitation on
>> earlier revisions.
>>
>> In DDR mode, the prescaler can divide by up to 512.
>>
>> The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
>> this change makes it possible to get 48 MHz from the USB PLL
>> (240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
>> (240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
>>
>> Signed-off-by: Benoît Thébaudeau <benoit@xxxxxxxxxxx>
>> Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
>> Reviewed-by: Fabio Estevam <fabio.estevam@xxxxxxx>
>> Signed-off-by: Ulf Hansson <ulf.hansson@xxxxxxxxxx>
>>
>> And indeed, after reverting this particular commit on top of 4.15.0-rc5, the problem goes away.
>>
>> This could be a clock rate tolerance issue with the particular brand/type of
>> SD card, however I've not experienced any issues with them before.
>
> [...]
>
> In a few words, looking at the reference manual of the i.MX53, there
> is an exception with its eSDHCv3: it does not allow SYSCTL.SDCLKFS =
> 0. It seems to be fine for the eSDHCv2 instances of the i.MX53 and for
> all the other i.MXs. So your issue can be fixed by changing the
> minimum legal prescaler value if eSDHCv3 is detected on i.MX53. I will
> send something for that. This should also be fixed in U-Boot.
Can you please try the change below? If it works and everyone is fine
with it, I will send a proper patch.
Best regards,
Benoît
---
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -687,6 +687,20 @@ static inline void esdhc_pltfm_set_clock(struct
sdhci_host *host,
return;
}
+ /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+ if (is_imx53_esdhc(imx_data)) {
+ /*
+ * According to the i.MX53 reference manual, if DLLCTRL[10] can
+ * be set, then the controller is eSDHCv3, else it is eSDHCv2.
+ */
+ val = readl(host->ioaddr + ESDHC_DLL_CTRL);
+ writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
+ temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
+ writel(val, host->ioaddr + ESDHC_DLL_CTRL);
+ if (temp & BIT(10))
+ pre_div = 2;
+ }
+
temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
| ESDHC_CLOCK_MASK);
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