Hello Ulf,
2015-08-26 0:27 GMT+09:00 Ulf Hansson <ulf.hansson@xxxxxxxxxx>:
> On 23 August 2015 at 14:58, Yoshihiro Kaneko <ykaneko0929@xxxxxxxxx> wrote:
>> From: Koji Matsuoka <koji.matsuoka.xm@xxxxxxxxxxx>
>>
>> The clock should be enable when SDHI registers are accessed.
>
> Yes, correct. But...
>
>>
>> Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@xxxxxxxxxxx>
>> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@xxxxxxxxx>
>> ---
>>
>> This patch is based on mmc-next branch of Ulf Hansson's mmc tree.
>>
>> * Perhaps this relates to the need to enhance clock management
>>
>> drivers/mmc/host/sh_mmcif.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
>> index 5a1fdd4..ad9ffea 100644
>> --- a/drivers/mmc/host/sh_mmcif.c
>> +++ b/drivers/mmc/host/sh_mmcif.c
>> @@ -1632,7 +1632,9 @@ static int sh_mmcif_suspend(struct device *dev)
>> {
>> struct sh_mmcif_host *host = dev_get_drvdata(dev);
>>
>> + pm_runtime_get_sync(dev);
>> sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
>> + pm_runtime_put(dev);
>
> ... when will the clock be gated, since the pm_runtime_put() here wont
> do the trick!
>
> That's a bit more complicated to deal with, but for now I will apply
> this patch as is.
Thanks!
I need to learn more.
Best Regards,
Kaneko
>
>>
>> return 0;
>> }
>> --
>> 1.9.1
>>
>
> Thanks, applied for next!
>
> Kind regards
> Uffe
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