From: Dinh Nguyen <dinguyen@xxxxxxxxxx> Hi, This is v2 of the patch series that makes the setting of the SDMMC_CMD_USE_HOLD_REG bit generic. v2 differences: * Another part of the spec on dw_mmc states, "Never set CMD.use_hold_reg = 1 and cclk_in_drv phase shift to 0 at the same time. This would add an extra one-cycle delay on the output path, resulting in incorrect behavior." The cclk_in_drv phase shift is the 2nd parameter in the "samsung,dw-mshc-sdr-timing" and "samsung,dw-mshc-ddr-timing" bindings. V2 checks for the cclk_in_drv phase shift value. If cclk_in_drv = 0, then we cannot set the SDMMC_CMD_USE_HOLD_REG bit. * Removes the Exynos' platform specific prepare_command's function that sets the SDMMC_CMD_USE_HOLD_REG based on the cclk_in_drv phase shift value. Thanks, Dinh Nguyen (3): mmc: dw_mmc: Enable the hold reg for certain speed modes mmc: dw_mmc-pltm: Remove Rockchip's custom dw_mmc driver structure mmc: dw_mmc-exynos: Remove Exynos' custom prepare_command function drivers/mmc/host/dw_mmc-exynos.c | 14 ------------ drivers/mmc/host/dw_mmc-pltfm.c | 12 +---------- drivers/mmc/host/dw_mmc.c | 44 ++++++++++++++++++++++++++++++++++++++ include/linux/mmc/dw_mmc.h | 3 +++ 4 files changed, 48 insertions(+), 25 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
