From: Dinh Nguyen <dinguyen@xxxxxxxxxx> Hi, This patch series makes the setting of the SDMMC_CMD_USE_HOLD_REG bit generic for all platforms that requires it. According the Synopsys spec on the dw_mmc, setting the SDMMC_CMD_USE_HOLD_REG should be done for all speeds except for the following higher speed modes: SDR104, SDR50, DDR50. I am also include MMC_HS200 speed as not needing the SDMMC_CMD_USE_HOLD_REG bit set as well. Currently, Rockchip and SOCFPGA's variant of the dw_mmc requires that the SDMMC_CMD_USE_HOLD_REG be set. For SOCFPGA, the dw_mmc is operating at MMC_TIMING_SD_HS mode. I don't know Rockchip's variant is operating at. Thanks, Dinh Nguyen (2): mmc: dw_mmc: Enable the hold reg for certain speed modes mmc: dw_mmc-pltm: Remove Rockchip's custom dw_mmc driver structure drivers/mmc/host/dw_mmc-pltfm.c | 12 +----------- drivers/mmc/host/dw_mmc.c | 14 ++++++++++++++ include/linux/mmc/dw_mmc.h | 1 + 3 files changed, 16 insertions(+), 11 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
