On Friday 06 December 2013, dinguyen@xxxxxxxxxx wrote: > From: Dinh Nguyen <dinguyen@xxxxxxxxxx> > > Hi, > > This patch series makes the setting of the SDMMC_CMD_USE_HOLD_REG bit generic > for all platforms that requires it. According the Synopsys spec on the dw_mmc, > setting the SDMMC_CMD_USE_HOLD_REG should be done for all speeds except for the > following higher speed modes: SDR104, SDR50, DDR50. I am also include MMC_HS200 > speed as not needing the SDMMC_CMD_USE_HOLD_REG bit set as well. > > Currently, Rockchip and SOCFPGA's variant of the dw_mmc requires that the > SDMMC_CMD_USE_HOLD_REG be set. For SOCFPGA, the dw_mmc is operating at > MMC_TIMING_SD_HS mode. I don't know Rockchip's variant is operating at. > Very nice, thanks for implementing this! Acked-by: Arnd Bergmann <arnd@xxxxxxxx> Obviously this needs to be tested on at least the rockchips variant, but ideally on most others too. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
