On Fri, Nov 22, 2024 at 12:49:45PM +0000, Damien Le Moal wrote: > On 11/22/24 21:38, Christoph Hellwig wrote: > > On Fri, Nov 22, 2024 at 12:25:19PM +0000, Lorenzo Stoakes wrote: > >> It's an ongoing maintenance burden, discussions about seeing whether it's > >> feasible to remove it have been had in multiple places. > >> > >> I have personally run into issues having to accommodate it on numerous > >> occasions, as have many others. > >> > >> I'd be interested to know which products specifically ship this and also > >> require tip kernel, perhaps this is just a case of my not being aware of > >> certain architectures? > > > > I can't tell you the products I know on commercial basis. Most of them > > are arm based, but I also know about at least one RISC-V one. They > > all used the latest long term stable at the time of release and tend > > to stay on that. And the involved vendors keep spinning out new versions > > of these every few years. > > To add to this, we had a discussion at the RISC-V MC at plumbers last year (I > think it was) about removing the K210 RISC-V SoC and associated RISC-V NOMMU > support. But several people complained about that because several FPGAs > implementing RISC-V cores are NOMMU (for obvious reasons for the FPGA case). So > NOMMU is being used out there. Thanks guys, appreciate the input, and this has made me aware of things I simply was not before. In that case, I am actually rather in favour of this series to make it easier to test nommu things :) > > -- > Damien Le Moal > Western Digital Research
