Quoting: https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/Virtual-Memory-System-Architecture--VMSA-/Memory-region-attributes/Long-descriptor-format-memory-region-attributes?lang=en#BEIIBEIJ "Contiguous hint The Long-descriptor translation table format descriptors contain a Contiguous hint bit. Setting this bit to 1 indicates that 16 adjacent translation table entries point to a contiguous output address range. These 16 entries must be aligned in the translation table so that the top 5 bits of their input addresses, that index their position in the translation table, are the same. For example, referring to Figure 12.21, to use this hint for a block of 16 entries in the third-level translation table, bits[20:16] of the input addresses for the 16 entries must be the same. The contiguous output address range must be aligned to size of 16 translation table entries at the same translation table level. Use of this hint means that the TLB can cache a single entry to cover the 16 translation table entries. This bit is only a hint bit. The architecture does not require a processor to cache TLB entries in this way. To avoid TLB coherency issues, any TLB maintenance by address must not assume any optimization of the TLB tables that might result from use of the hint bit.
