Re: AMD SEV-SNP/Intel TDX: validation of memory pages

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On Tue, Feb 16, 2021 at 04:59:52PM +0100, Paolo Bonzini wrote:
> - the inner handler does nothing but telling the outer handler to rerun.
> The way it does it is certainly not pretty, because it has to work at any
> instruction boundary, but at its heart it's basically a do{}while loop.

That only works if processing of all inner #VE can be deferred, which is
not the case for instruction emulation #VEs like MSR accesses, io-port
or MMIO accesses. I guess those could all be replaced direct TDCALLs,
but the question remains whether this is possible with MSR accesses, means
that the list of MSRs which will cause #VEs is statically defined and
doesn't change between hypervisors. All in all this sounds hard to
maintain and easy to break by unrelated changes.

Regards,

	Joerg




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