Hi, On Wed, Nov 11, 2020 at 08:52:00AM +0200, Mike Rapoport wrote: > Hi, > > On Tue, Nov 10, 2020 at 03:36:20PM -0800, Minchan Kim wrote: > > On Tue, Nov 10, 2020 at 06:21:55PM +0200, Mike Rapoport wrote: > > > On Tue, Nov 10, 2020 at 12:21:11PM +0100, Arnd Bergmann wrote: > > > > On Tue, Nov 10, 2020 at 10:58 AM Mike Rapoport <rppt@xxxxxxxxxx> wrote: > > > > > > > > > > > > > > asm/sparsemem.h is not available on some architectures. > > > > > > > It's better to use linux/mmzone.h instead. > > > > > > > > Ah, I missed that, too. > > > > > > > > > > Hm, linux/mmzone.h only includes asm/sparsemem.h when CONFIG_SPARSEMEM > > > > > > is enabled. However, on ARM at least I can have configurations without > > > > > > CONFIG_SPARSEMEM and physical address extension on (e.g. > > > > > > multi_v7_defconfig + CONFIG_LPAE + CONFIG_ZSMALLOC). > > > > > > > > > > > > While sparsemem seems to be a good idea with LPAE it really seems not > > > > > > required (see also https://lore.kernel.org/patchwork/patch/567589/). > > > > > > > > > > > > There seem to be also other architectures which define MAX_PHYSMEM_BITS > > > > > > only when SPARSEMEM is enabled, e.g. > > > > > > arch/riscv/include/asm/sparsemem.h... > > > > > > > > > > > > Not sure how to get out of this.. Maybe make ZSMALLOC dependent on > > > > > > SPARSEMEM? It feels a bit silly restricting ZSMALLOC selection only due > > > > > > to a compile time define... > > > > > > > > > > I think we can define MAX_POSSIBLE_PHYSMEM_BITS in one of > > > > > arch/arm/inclide/asm/pgtable-{2,3}level-*.h headers to values supported > > > > > by !LPAE and LPAE. > > > > > > > > Good idea. I wonder what other architectures need the same though. > > > > Here are some I found: > > > > > > > > $ git grep -l PHYS_ADDR_T_64BIT arch | grep Kconfig > > > > arch/arc/Kconfig > > > > arch/arm/mm/Kconfig > > > > arch/mips/Kconfig > > > > arch/powerpc/platforms/Kconfig.cputype > > > > arch/x86/Kconfig > > > > > > > > arch/arc has a CONFIG_ARC_HAS_PAE40 option > > > > arch/riscv has 34-bit addressing in rv32 mode > > > > arch/mips has up to 40 bits with mips32r3 XPA, but I don't know what > > > > supports that > > > > > > > > arch/powerpc has this: > > > > config PHYS_64BIT > > > > bool 'Large physical address support' if E500 || PPC_86xx > > > > depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx > > > > > > > > Apparently all three (4xx, e500v2, mpc86xx/e600) do 36-bit physical > > > > addressing, but each one has a different page table format. > > > > > > > > Microblaze has physical address extensions, but neither those nor > > > > 64-bit mode have so far made it into the kernel. > > > > > > > > To be on the safe side, we could provoke a compile-time error > > > > when CONFIG_PHYS_ADDR_T_64BIT is set on a 32-bit > > > > architecture, but MAX_POSSIBLE_PHYSMEM_BITS is not set. > > > > > > Maybe compile time warning and a runtime error in zs_init() if 32 bit > > > machine has memory above 4G? > > > > I guess max_pfn will represent maximum pfn configued in the system > > and will not be changed in the runtime. If it's true, how about this? > > (didn't test at all but just for RFC) > > Largely, max_pfn is the maximal pfn at boot time but I don't think it > can be used on systems with memory hotplug. Unless I'm missing > something, with memory hotplug we must have compile-time maximum. > Make sense. I am looking forward to seeing Arnd's patches at this moment. Thanks! Thanks for the help!
