On Tue, Nov 10, 2020 at 10:58 AM Mike Rapoport <rppt@xxxxxxxxxx> wrote: > > > > > > asm/sparsemem.h is not available on some architectures. > > > It's better to use linux/mmzone.h instead. Ah, I missed that, too. > > Hm, linux/mmzone.h only includes asm/sparsemem.h when CONFIG_SPARSEMEM > > is enabled. However, on ARM at least I can have configurations without > > CONFIG_SPARSEMEM and physical address extension on (e.g. > > multi_v7_defconfig + CONFIG_LPAE + CONFIG_ZSMALLOC). > > > > While sparsemem seems to be a good idea with LPAE it really seems not > > required (see also https://lore.kernel.org/patchwork/patch/567589/). > > > > There seem to be also other architectures which define MAX_PHYSMEM_BITS > > only when SPARSEMEM is enabled, e.g. > > arch/riscv/include/asm/sparsemem.h... > > > > Not sure how to get out of this.. Maybe make ZSMALLOC dependent on > > SPARSEMEM? It feels a bit silly restricting ZSMALLOC selection only due > > to a compile time define... > > I think we can define MAX_POSSIBLE_PHYSMEM_BITS in one of > arch/arm/inclide/asm/pgtable-{2,3}level-*.h headers to values supported > by !LPAE and LPAE. Good idea. I wonder what other architectures need the same though. Here are some I found: $ git grep -l PHYS_ADDR_T_64BIT arch | grep Kconfig arch/arc/Kconfig arch/arm/mm/Kconfig arch/mips/Kconfig arch/powerpc/platforms/Kconfig.cputype arch/x86/Kconfig arch/arc has a CONFIG_ARC_HAS_PAE40 option arch/riscv has 34-bit addressing in rv32 mode arch/mips has up to 40 bits with mips32r3 XPA, but I don't know what supports that arch/powerpc has this: config PHYS_64BIT bool 'Large physical address support' if E500 || PPC_86xx depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx Apparently all three (4xx, e500v2, mpc86xx/e600) do 36-bit physical addressing, but each one has a different page table format. Microblaze has physical address extensions, but neither those nor 64-bit mode have so far made it into the kernel. To be on the safe side, we could provoke a compile-time error when CONFIG_PHYS_ADDR_T_64BIT is set on a 32-bit architecture, but MAX_POSSIBLE_PHYSMEM_BITS is not set. > That's what x86 does: > > $ git grep -w MAX_POSSIBLE_PHYSMEM_BITS arch/ > arch/x86/include/asm/pgtable-3level_types.h:#define MAX_POSSIBLE_PHYSMEM_BITS 36 Doesn't x86 also support a 40-bit addressing mode? I suppose those machines that actually used it are long gone. > arch/x86/include/asm/pgtable_64_types.h:#define MAX_POSSIBLE_PHYSMEM_BITS 52 > > It seems that actual numbers would be 36 for !LPAE and 40 for LPAE, but > I'm not sure about that. Close enough, yes. The 36-bit addressing is on !LPAE is only used for early static mappings, so I think we can pretend it's always 32-bit. I checked the ARMv8 reference, and it says that ARMv8-Aarch32 actually supports 40 bit physical addressing both with non-LPAE superpages (short descriptor format) and LPAE (long descriptor format), but Linux only does 36-bit addressing on superpages as specified for ARMv6/ARMv7 short descriptors. Arnd
