> 2023年5月16日 21:47，Maciej W. Rozycki <macro@xxxxxxxxxxx> 写道： > > On Tue, 16 May 2023, Jiaxun Yang wrote: > >>> Actually the MIPS MT ASE is explicitly from R2 onwards only[1] and it has >>> *not* been withdrawn as at R6[2]. >> >> Thanks for the info! >> >> I’m a little bit confused with relationship of MT and VP though, I thought VP >> suppressed MT, and they look conflicting, does it mean there are two possible >> ways of multithreading in R6? > > Hmm, interesting point. I would have thought you can have either but not > both, however there is a note along with the description of CP0.Config3.MT > in[1] that for R6 the bit has to be 0. That place and the description of > the new CP0.Config5.VP bit seem the only mentions of MT ASE/Module removal > with R6 and there is e.g. this paragraph for CP0.Wired: I’ve heard back from hardware guys, the stated that MT and VP are exclusive but we should not assume VP as only multithreading implementation on R6 (in term of privileged architecture). Actually I7200 (nanoMIPS) follows R6 privileged spec (Config.AR = 2) but have MT implemented rather than VP. However they assured me that *application processor* level cores that is expected to run Linux in future will only implement VP, so we can omit combination of MT and R6 in kernel. Just perform some basic checks to prevent hardware guys change their mind in future. […] Thanks - Jiaxun
