On Tue, 16 May 2023, Jiaxun Yang wrote:
> > Actually the MIPS MT ASE is explicitly from R2 onwards only[1] and it has
> > *not* been withdrawn as at R6[2].
>
> Thanks for the info!
>
> I’m a little bit confused with relationship of MT and VP though, I thought VP
> suppressed MT, and they look conflicting, does it mean there are two possible
> ways of multithreading in R6?
Hmm, interesting point. I would have thought you can have either but not
both, however there is a note along with the description of CP0.Config3.MT
in[1] that for R6 the bit has to be 0. That place and the description of
the new CP0.Config5.VP bit seem the only mentions of MT ASE/Module removal
with R6 and there is e.g. this paragraph for CP0.Wired:
"Release 6 adds the Limit field. The intent of a non-zero value for this
field is to place a limit on the number of wired entries in a TLB such
that non-wired entries may be shared in a common physical TLB by multiple
VPEs (as defined in the Multi-threading (MT) Module, Volume IV-f), or
Guests and Root (see the Virtualization Module, Volume IV-i). For Release
6, if the Limit field is greater than 0, and a value greater than Limit is
written to the Wired field, then the write is ignored."
which explicitly refers to the MT ASE/Module in the context of R6 only.
Revision 6.02 is the only MIPS32r6 privileged specification a copy of
which I have, however it has this note in the revision history:
"* Added CP0 VPControl for MT (new)"
so I guess support for the MT ASE/Module was removed as an afterthought
and then the architecture specification updated in a sloppy manner.
And indeed the MIPS64r6 privileged specification confirms that, as I have
copies or revisions 6.00 and 6.03, and the former has the MT ASE/Module
still fully supported (and no mention of the CP0.Config5.VP bit nor the
CP0.VPControl register) while the latter is similar to MIPS32 revision
6.02 document.
> If so I’d probably rewrite cps-sec in uasm to take that into account, sigh.
I guess you don't have to be concerned about R6 then.
[1] "MIPS32 Architecture For Programmers, Vol. III: MIPS32 / microMIPS32
Privileged Resource Architecture", IMAGINATION TECHNOLOGIES, Document
Number: MD00090, Revision 6.02, July 10, 2015, Table 9.67 "Config3
Register Field Descriptions", p. 251
Maciej
