On Thu, Apr 20, 2023, Thomas Gleixner wrote: > On Thu, Apr 20 2023 at 10:23, Andrew Cooper wrote: > > On 20/04/2023 9:32 am, Thomas Gleixner wrote: > > > On Wed, Apr 19, 2023, Andrew Cooper wrote: > > > > This was changed in x2APIC, which made the x2APIC_ID immutable. > > >> I'm pondering to simply deny parallel mode if x2APIC is not there. > > > > I'm not sure if that will help much. > > Spoilsport. LOL, well let me pile on then. x2APIC IDs aren't immutable on AMD hardware. The ID is read-only when the CPU is in x2APIC mode, but any changes made to the ID while the CPU is in xAPIC mode survive the transition to x2APIC. From the APM: A value previously written by software to the 8-bit APIC_ID register (MMIO offset 30h) is converted by hardware into the appropriate format and reflected into the 32-bit x2APIC_ID register (MSR 802h). FWIW, my observations from testing on bare metal are that the xAPIC ID is effectively read-only (writes are dropped) on Intel CPUs as far back as Haswell, while the above behavior described in the APM holds true on at least Rome and Milan. My guess is that Intel's uArch specific behavior of the xAPIC ID being read-only was introduced when x2APIC came along, but I didn't test farther back than Haswell.
