Hi,
On 7/7/22 17:12, Sander Vanheule wrote:
On Thu, 2022-07-07 at 16:39 +0200, Thomas Bogendoerfer wrote:
On Thu, Jul 07, 2022 at 02:57:15PM +0200, Martin Blumenstingl wrote:
IMHO there is the problem, irq-mips-cpu.c can only do CPU irq operations
on the same CPU. I've checked MIPS MT specs and it's possible do
modify CP0 registers between VPEs. Using that needs changes in
irq-mips-cpu.c. But mabye that's not woth the effort as probably
all SMP cabable platforms have some multi processort capable
interrupt controller implemented.
Not sure I can be of much help. That the patch works on the RTL SoCs is
mostly empirical and was found in the vendor code.
My understanding from the MIPS documentation is that it is not specified
what happens when a multi VPE capable IRQ controller triggers CPU
interrupts: if multiple VPEs are possible targets, then it is not
defined whether one of them gets them (and which one), multiple, or all.
So trying to control what happens between VPEs is probably SoC-dependent
functionality.
Cheers,
Birger
