On Thu, Jul 7, 2022 at 12:11 PM Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx> wrote: [...] > > - why can MIPS CPU interrupt 6 and 7 be enabled unconditionally while > > 2-5 cannot be enabled unconditionally? > > 7 is timer interrupt and is usually wired for 34K cpus and 6 is > performance counter hopefully handled as well. And I agree that > this still isn't the best approach here Thanks for this explanation! > > - seeing that there's also a mips_gic_present() check in the opposite > > case of what Aleksander's patch modifies: does this indicate that > > unmasking CPU interrupt lines for VPE 1 is not handled by the MIPS CPU > > interrupt controller driver at all at this point (and if so: do you > > have any suggestions how to properly fix this)? > > I haven't checked how GIC is integrated. Iirc it does something similair > to Lantiq's irq controller and hides all CPU internal interrupts behind > it. > > So I see two solutions for your problem. > > 1. Add "mti,cpu-interrupt-controller" to the DT and wire it up I think this is the preferred way. I tried this before (if you are curious, see [0] and [1]) and it didn't work. Are you aware of any MIPS SoC with upstream drivers which do have working IRQs on VPE 1? Or can you point me to the code in drivers/irqchip/irq-mips-cpu.c that's responsible for enabling the interrupts on VPE 1 (is it simply unmask_mips_irq)? > 2. Create your own struct plat_smp_ops using vsmp_smp_ops as > a template and overload .boot_secondary This would work, but: personally I would like to remove as much Lantiq platform specific code as possible so it's easier to maintain. Best regards, Martin [0] https://github.com/xdarklight/linux/commit/0e5a5dda0e999a3a2e5a81324fef15405d8c6b4a [1] https://github.com/xdarklight/linux/commit/97ec4689d2016606442577988d28fef6728c3bbf
