On Wed, Jul 06, 2022 at 11:56:47AM +0200, Martin Blumenstingl wrote: > Without this patch all interrupts are fine on VPE 0 and with SMP disabled. I fully understand the problem. But not everybody uses this interrupt setup, so changing generic code will have effects there too. > - why can MIPS CPU interrupt 6 and 7 be enabled unconditionally while > 2-5 cannot be enabled unconditionally? 7 is timer interrupt and is usually wired for 34K cpus and 6 is performance counter hopefully handled as well. And I agree that this still isn't the best approach here > - seeing that there's also a mips_gic_present() check in the opposite > case of what Aleksander's patch modifies: does this indicate that > unmasking CPU interrupt lines for VPE 1 is not handled by the MIPS CPU > interrupt controller driver at all at this point (and if so: do you > have any suggestions how to properly fix this)? I haven't checked how GIC is integrated. Iirc it does something similair to Lantiq's irq controller and hides all CPU internal interrupts behind it. So I see two solutions for your problem. 1. Add "mti,cpu-interrupt-controller" to the DT and wire it up 2. Create your own struct plat_smp_ops using vsmp_smp_ops as a template and overload .boot_secondary Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
