On Fri, Aug 21, 2020 at 11:12:28AM +0800, Heiher wrote: > MIPS ISA defines several types of memory barrier, of which Type-0 (full barrier) > is required, and the others are optional. In some vendor implementation (such as > Loongson), all optional parts are implemented to emit an illegal instruction > exception. Here, emulate to full barrier to ensure the functional semantics. > > If an implementation does not support SYNC 0, it should also not support SMP, so > the `smp_mb()` is only a compilation barrier. I see your point, but isn't taking an exception already more than a compiler barrier ? Does the missing sync hurt in real life ? Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
