MIPS ISA defines several types of memory barrier, of which Type-0 (full barrier)
is required, and the others are optional. In some vendor implementation (such as
Loongson), all optional parts are implemented to emit an illegal instruction
exception. Here, emulate to full barrier to ensure the functional semantics.
If an implementation does not support SYNC 0, it should also not support SMP, so
the `smp_mb()` is only a compilation barrier.
Signed-off-by: Heiher <r@xxxxxx>
---
arch/mips/kernel/traps.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 38aa07ccdbcc..d63e8671e9d2 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -501,6 +501,7 @@ asmlinkage void do_be(struct pt_regs *regs)
#define RD 0x0000f800
#define FUNC 0x0000003f
#define SYNC 0x0000000f
+#define STYPE 0x000007c0
#define RDHWR 0x0000003b
/* microMIPS definitions */
@@ -688,6 +689,8 @@ static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
{
if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
+ if ((opcode & STYPE) != 0)
+ smp_mb();
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
1, regs, 0);
return 0;
--
2.28.0
