On 20/06/18 18:27, Christoph Hellwig wrote:
On Wed, Jun 20, 2018 at 05:04:00PM +1000, Greg Ungerer wrote:
The fec drivers uses dma_alloc_coherent for the TX descriptors,
but I don't really see any manual cache maintainance in it.
What do I miss?
No, your right, I missed that. I don't see anything in the ColdFire
doco that indicates that there is any coherency on the FEC module
on the more advanced parts with cache. So I suspect that is a real
problem (not one that anyone has reported in practice yet though...)
Or these devices always hit the
if (((unsigned long)bufaddr) & fep->tx_align ||
fep->quirks & FEC_QUIRK_SWAP_FRAME) {
case?
Possibly also that in no-MMU mode the normal cache mode on
ColdFire is write-through, so no real need for a cache flush.
There is also at least one odd looking flush on the receive path:
#ifdef CONFIG_M532x
flush_cache_all();
#endif
And the general cache flushing support functions are not really
very fine grained for ColdFire anyway.
Regards
Greg
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