Hi Christoph, On 19/06/18 17:07, Christoph Hellwig wrote:
m68 is normally not dma cache coherent, and thus requires invalidating or writing back caches in DMA, which is handled in the m68k_dma_sync_single_for_device routine. For coherent mappings the code sets up a non-cachable mapping in m68k_dma_alloc. Except that for the nommu or coldfire code it doesn't and just does a plain old page allocation without any caching magic. Does this mean coldfire and the nommu case in general do not actually require cache coherency and don't need the cache maintainance on the dma mapping operations either?
For the nommu case there is no magic because there is no underlying pages or page table entries to set any control bits for. There is no fine grained control, just a couple of cache enabled regions (such as all of RAM) and some bulk control (such as invalidate and clear). But it does still require cache maintenance for dma operations. For example the drivers/net/ethernet/freescale/fec_main.c driver is common on ColdFire SoC parts and it needs to do all the appropriate dma operations to work right. Though on some of the older simpler parts (5752 for example) there ins only instruction cache and you don't have to do dma operations on it. For the ColdFire with MMU enabled case I am not entirely sure now why we don't go through something similar in m68k_dma_alloc() as the classic m68k CPUs do. Regards Greg -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
