On 2/21/25 3:09 AM, Eason Yang wrote:
> Add Nuvoton NCT7201/NCT7202 system voltage monitor 12-bit ADC driver
>
> NCT7201/NCT7202 supports up to 12 analog voltage monitor inputs and up to
> 4 SMBus addresses by ADDR pin. Meanwhile, ALERT# hardware event pins for
> independent alarm signals, and the all threshold values could be set for
> system protection without any timing delay. It also supports reset input
> RSTIN# to recover system from a fault condition.
>
> Currently, only single-edge mode conversion and threshold events support.
>
> Signed-off-by: Eason Yang <j2anfernee@xxxxxxxxx>
> ---
> MAINTAINERS | 1 +
> drivers/iio/adc/Kconfig | 11 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/nct7201.c | 487 ++++++++++++++++++++++++++++++++++++++
> 4 files changed, 500 insertions(+)
> create mode 100644 drivers/iio/adc/nct7201.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fdc4aa5c7eff..389cbbdae1a7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2838,6 +2838,7 @@ F: arch/arm/mach-npcm/
> F: arch/arm64/boot/dts/nuvoton/
> F: drivers/*/*/*npcm*
> F: drivers/*/*npcm*
> +F: drivers/iio/adc/nct7201.c
Same comment as DT bindings, this is ARM/NUVOTON NPCM ARCHITECTURE.
We need a new section for this chip since it is stand-alone.
> F: drivers/rtc/rtc-nct3018y.c
> F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
> F: include/dt-bindings/clock/nuvoton,npcm845-clk.h
...
> diff --git a/drivers/iio/adc/nct7201.c b/drivers/iio/adc/nct7201.c
> new file mode 100644
> index 000000000000..c5d1540bcc00
> --- /dev/null
> +++ b/drivers/iio/adc/nct7201.c
> @@ -0,0 +1,487 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Driver for Nuvoton nct7201 and nct7202 power monitor chips.
> + *
> + * Copyright (c) 2024-2025 Nuvoton Technology corporation.
> + */
> +
> +#include <linux/array_size.h>
> +#include <linux/bits.h>
> +#include <linux/cleanup.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/i2c.h>
> +#include <linux/init.h>
Are we really using something from the init header?
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/regmap.h>
> +#include <linux/types.h>
> +#include <linux/unaligned.h>
> +
> +#include <linux/iio/events.h>
> +#include <linux/iio/iio.h>
> +
...
> +static int nct7201_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long mask)
> +{
> + u16 volt;
> + unsigned int value;
> + int err;
> + struct nct7201_chip_info *chip = iio_priv(indio_dev);
> +
> + if (chan->type != IIO_VOLTAGE)
> + return -EOPNOTSUPP;
> +
> + guard(mutex)(&chip->access_lock);
The regmap should already have an intneral lock, so this mutex seems
reduandnt in it's current usage.
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + err = regmap_read(chip->regmap16, NCT7201_REG_VIN(chan->address), &value);
> + if (err < 0)
> + return err;
> + volt = value;
> + *val = FIELD_GET(NCT7201_REG_VIN_MASK, volt);
> + return IIO_VAL_INT;
> + case IIO_CHAN_INFO_SCALE:
> + /* From the datasheet, we have to multiply by 0.0004995 */
> + *val = 0;
> + *val2 = 499500;
> + return IIO_VAL_INT_PLUS_NANO;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int nct7201_read_event_value(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum iio_event_type type,
> + enum iio_event_direction dir,
> + enum iio_event_info info,
> + int *val, int *val2)
> +{
> + struct nct7201_chip_info *chip = iio_priv(indio_dev);
> + u16 volt;
> + unsigned int value;
> + int err;
> +
> + if (chan->type != IIO_VOLTAGE)
> + return -EOPNOTSUPP;
> +
> + if (info != IIO_EV_INFO_VALUE)
> + return -EINVAL;
> +
> + if (dir == IIO_EV_DIR_FALLING) {
> + err = regmap_read(chip->regmap16, NCT7201_REG_VIN_LOW_LIMIT(chan->address),
> + &value);
> + if (err < 0)
> + return err;
> + volt = value;
Assigning to volt seems reduant. We can just pass value to
FIELD_GET() below.
> + } else {
> + err = regmap_read(chip->regmap16, NCT7201_REG_VIN_HIGH_LIMIT(chan->address),
> + &value);
> + if (err < 0)
> + return err;
> + volt = value;
> + }
> +
> + *val = FIELD_GET(NCT7201_REG_VIN_MASK, volt);
> +
> + return IIO_VAL_INT;
> +}
> +
> +static int nct7201_write_event_value(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum iio_event_type type,
> + enum iio_event_direction dir,
> + enum iio_event_info info,
> + int val, int val2)
> +{
> + struct nct7201_chip_info *chip = iio_priv(indio_dev);
> +
> + if (chan->type != IIO_VOLTAGE)
> + return -EOPNOTSUPP;
> +
> + if (info != IIO_EV_INFO_VALUE)
> + return -EOPNOTSUPP;
> +
> + if (dir == IIO_EV_DIR_FALLING)
> + regmap_write(chip->regmap16, NCT7201_REG_VIN_LOW_LIMIT(chan->address),
> + FIELD_PREP(NCT7201_REG_VIN_MASK, val));
No error checking? Could just return here directly.
> + else
> + regmap_write(chip->regmap16, NCT7201_REG_VIN_HIGH_LIMIT(chan->address),
> + FIELD_PREP(NCT7201_REG_VIN_MASK, val));
> +
> + return 0;
> +}
> +
...
> +static int nct7201_write_event_config(struct iio_dev *indio_dev,
> + const struct iio_chan_spec *chan,
> + enum iio_event_type type,
> + enum iio_event_direction dir,
> + bool state)
> +{
> + struct nct7201_chip_info *chip = iio_priv(indio_dev);
> + unsigned int mask;
> +
> + if (chan->type != IIO_VOLTAGE)
> + return -EOPNOTSUPP;
> +
> + mask = BIT(chan->address);
> +
> + if (!state && (chip->vin_mask & mask))
> + chip->vin_mask &= ~mask;
> + else if (state && !(chip->vin_mask & mask))
> + chip->vin_mask |= mask;
This would be easier to read as:
if (state)
chip->vin_mask |= mask;
else
chip->vin_mask &= ~mask;
> +
> + if (chip->num_vin_channels <= 8)
> + regmap_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE_1, chip->vin_mask);
No error checking?
> + else
> + regmap_bulk_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE_1,
> + &chip->vin_mask, sizeof(chip->vin_mask));
> +
> + return 0;
> +}
> +
...
> +static int nct7201_init_chip(struct nct7201_chip_info *chip)
> +{
> + u8 data[2];
> + unsigned int value;
> + int err;
> +
> + regmap_write(chip->regmap, NCT7201_REG_CONFIGURATION,
> + NCT7201_BIT_CONFIGURATION_RESET);
Check error return?
> +
> + /*
> + * After about 25 msecs, the device should be ready and then
> + * the Power Up bit will be set to 1. If not, wait for it.
> + */
> + mdelay(25);
> + err = regmap_read(chip->regmap, NCT7201_REG_BUSY_STATUS, &value);
> + if (err < 0)
> + return err;
> + if (!(value & NCT7201_BIT_PWR_UP))
> + return dev_err_probe(&chip->client->dev, -EIO,
> + "Failed to power up after reset\n");
> +
> + /* Enable Channel */
> + if (chip->num_vin_channels <= 8) {
> + data[0] = NCT7201_REG_CHANNEL_ENABLE_1_MASK;
> + err = regmap_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE_1, data[0]);
> + if (err < 0)
> + return dev_err_probe(&chip->client->dev, -EIO,
> + "Failed to write NCT7201_REG_CHANNEL_ENABLE_1\n");
> + } else {
> + data[0] = NCT7201_REG_CHANNEL_ENABLE_1_MASK;
> + data[1] = NCT7201_REG_CHANNEL_ENABLE_2_MASK;
> + err = regmap_bulk_write(chip->regmap, NCT7201_REG_CHANNEL_ENABLE_1,
> + data, ARRAY_SIZE(data));
> + if (err < 0)
> + return dev_err_probe(&chip->client->dev, -EIO,
> + "Failed to write NCT7201_REG_CHANNEL_ENABLE_1 and NCT7201_REG_CHANNEL_ENABLE_2\n");
> + }
> +
> + value = get_unaligned_le16(data);
Does it matter that data[1] may be uninitialized and contain random value here?
> + chip->vin_mask = value;
Don't really need the intermediate value assignment here.
> +
> + /* Start monitoring if needed */
> + err = regmap_read(chip->regmap, NCT7201_REG_CONFIGURATION, &value);
> + if (err < 0)
> + return dev_err_probe(&chip->client->dev, -EIO,
> + "Failed to read NCT7201_REG_CONFIGURATION\n");
> +
> + regmap_set_bits(chip->regmap, NCT7201_REG_CONFIGURATION, NCT7201_BIT_CONFIGURATION_START);
> +
> + return 0;
> +}
> +
