On Wed, 30 Oct 2024 14:04:58 +0100 Nuno Sá <noname.nuno@xxxxxxxxx> wrote: > On Mon, 2024-10-28 at 17:07 +0100, Uwe Kleine-König wrote: > > Some of the ADCs by Analog signal their irq condition on the MISO line. > > So typically that line is connected to an SPI controller and a GPIO. The > > GPIO is used as input and the respective interrupt is enabled when the > > last SPI transfer is completed. > > > > Depending on the GPIO controller the toggling MISO line might make the > > interrupt pending even while it's masked. In that case the irq handler > > is called immediately after irq_enable() and so before the device > > actually pulls that line low which results in non-sense values being > > reported to the upper layers. > > > > The only way to find out if the line was actually pulled low is to read > > the GPIO. (There is a flag in AD7124's status register that also signals > > if an interrupt was asserted, but reading that register toggles the MISO > > line and so might trigger another spurious interrupt.) > > > > Add the possibility to specify an interrupt GPIO in the machine > > description instead of a plain interrupt. This GPIO is used as interrupt > > source and to check if the irq line is actually active in the irq > > handler. > > > > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxx> > > --- > > Hi all, > > Regarding this, I do share some of the concerns already raised by Jonathan. I fear > that we're papering around an issue with the IRQ controller rather than being an > issue with the device. When I look at irq_disable() docs [1], it feels that we're > already doing what we're supposed to do. IOW, we disable the lazy approach so we > *should* not get any pending IRQ. Also looking at drivers as the xilinx gpio > controller, it seems some are careful about this [2] and make sure to clear all > pending IRQs when unmasking. Your links are both to the same place. > > Jonathan also said this: > > "True enough - that race is a possibility, but not all interrupt inputs > are capable of gpio usage whilst setup to received interrupts." Race should be easy to avoid using a level interrupt now I think more on that: can't miss a level. > > To my understanding this also means this is doomed to fail for some devices or am I > not following it? If you were wired to one of those, you couldn't use the GPIO trick, but then don't have a GPIO in your DT in that case. > > All that said, my naive feeling would be for a masked line to not get any pending IRQ > and if it does, the driver should make sure to clean all outstanding interrupts when > unmasking. But I'm far from being an expert of the IRQ subsystem. Maybe it would be > interesting to get some inputs about someone who actually knows better? +CC Thomas Gleixner, Hi Thomas, Annoying case where a wire is both the interrupt source for dataready and the SPI data line (if separate clock signal is toggling) So currently the driver masks interrupts at the host end, but we have at least one interrupt controller where they end up pending and fire on reenabling the interrupt. Querying the device to check the status register then ends up causing it to happen again, so that doesn't help. Proposal is to query it as a GPIO (or maybe a separate GPIO wired to the same pin) to check the level when an interrupt comes in. Any thoughts on this nasty hardware and what is responsiblity of the device driver vs the interrupt controller driver in this case? Jonathan > > [1]: https://elixir.bootlin.com/linux/v6.11.5/source/kernel/irq/chip.c#L366 > [2]: https://elixir.bootlin.com/linux/v6.11.5/source/kernel/irq/chip.c#L366 > > - Nuno Sá > >
