On Thu, 2024-10-24 at 11:28 +0200, Angelo Dureghello wrote: > Hi Conor, > > On 22.10.2024 18:22, Conor Dooley wrote: > > On Mon, Oct 21, 2024 at 02:40:12PM +0200, Angelo Dureghello wrote: > > > From: Angelo Dureghello <adureghello@xxxxxxxxxxxx> > > > > > > Add a new compatible and related bindigns for the fpga-based > > > "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. > > > > > > The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the > > > generic AXI "DAC" IP, intended to control ad3552r and similar chips, > > > mainly to reach high speed transfer rates using a QSPI DDR > > > (dobule-data-rate) interface. > > > > > > The ad3552r device is defined as a child of the AXI DAC, that in > > > this case is acting as an SPI controller. > > > > > > Note, #io-backend is present because it is possible (in theory anyway) > > > to use a separate controller for the control path than that used > > > for the datapath. > > > > > > Signed-off-by: Angelo Dureghello <adureghello@xxxxxxxxxxxx> > > > --- > > > .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 69 +++++++++++++++++++++- > > > 1 file changed, 66 insertions(+), 3 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > index a55e9bfc66d7..0aabb210f26d 100644 > > > --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > > @@ -19,11 +19,13 @@ description: | > > > memory via DMA into the DAC. > > > > > > https://wiki.analog.com/resources/fpga/docs/axi_dac_ip > > > + https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html > > > > > > properties: > > > compatible: > > > enum: > > > - adi,axi-dac-9.1.b > > > + - adi,axi-ad3552r > > > > > > reg: > > > maxItems: 1 > > > @@ -36,7 +38,12 @@ properties: > > > - const: tx > > > > > > clocks: > > > - maxItems: 1 > > > + minItems: 1 > > > + maxItems: 2 > > > + > > > + clock-names: > > > + minItems: 1 > > > + maxItems: 2 > > > > > > '#io-backend-cells': > > > const: 0 > > > @@ -47,7 +54,31 @@ required: > > > - reg > > > - clocks > > > > > > -additionalProperties: false > > > +allOf: > > > + - if: > > > + properties: > > > + compatible: > > > + contains: > > > + const: adi,axi-ad3552r > > > + then: > > > + $ref: /schemas/spi/spi-controller.yaml# > > > + properties: > > > + clocks: > > > + minItems: 2 > > > + maxItems: 2 > > > > Is this maxItems required? It matches the outer maximum. > > > > > + clock-names: > > > + items: > > > + - const: s_axi_aclk > > > + - const: dac_clk > > > > The names are the same in both cases, you can move the definitions > > outside of the if/then/else stuff and only constrain it here. > > > thanks, could you maybe have a look if it's ok now ? > (maxItems not needed for a const list) > > clocks: > minItems: 1 > maxItems: 2 > > clock-names: > items: > - const: s_axi_aclk > - const: dac_clk > minItems: 1 > > '#io-backend-cells': > const: 0 > > required: > - compatible > - dmas > - reg > - clocks > > allOf: > - if: > properties: > compatible: > contains: > const: adi,axi-ad3552r > then: > $ref: /schemas/spi/spi-controller.yaml# > properties: > clocks: > minItems: 2 > clock-names: > minItems: 2 > else: > properties: > clocks: > maxItems: 1 > clock-names: > maxItems: 1 I guess in this case it could even be clock-names: false. One does not make much sense. - Nuno Sá
