On Fri, 2024-03-29 at 13:46 -0500, David Lechner wrote: > On Thu, Mar 28, 2024 at 8:22 AM Nuno Sa via B4 Relay > <devnull+nuno.sa.analog.com@xxxxxxxxxx> wrote: > > > > From: Nuno Sa <nuno.sa@xxxxxxxxxx> > > > > This adds the bindings documentation for the AXI DAC driver. > > > > Signed-off-by: Nuno Sa <nuno.sa@xxxxxxxxxx> > > --- > > .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 62 ++++++++++++++++++++++ > > MAINTAINERS | 7 +++ > > 2 files changed, 69 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > new file mode 100644 > > index 000000000000..1018fd274f04 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml > > @@ -0,0 +1,62 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Analog Devices AXI DAC IP core > > + > > +maintainers: > > + - Nuno Sa <nuno.sa@xxxxxxxxxx> > > + > > +description: | > > + Analog Devices Generic AXI DAC IP core for interfacing a DAC device > > + with a high speed serial (JESD204B/C) or source synchronous parallel > > + interface (LVDS/CMOS). > > + Usually, some other interface type (i.e SPI) is used as a control > > + interface for the actual DAC, while this IP core will interface > > + to the data-lines of the DAC and handle the streaming of data into > > + memory via DMA. > > Isn't it the other way around for DAC, from memory to hardware? Good catch! Yes, copy paste from the axi-adc and obviously missed this :) - Nuno Sá
