On Sun, Apr 02, 2023 at 05:46:57PM +0100, Jonathan Cameron wrote: > > > > > + .wr_table = &aio_ctl_wr_table, > > > > + .rd_table = &aio_ctl_rd_table, > > > > + .volatile_table = &aio_ctl_volatile_table, > > > > + .cache_type = REGCACHE_FLAT, > > > > +}; > > > > > > Do we need regmap lock? > > > > I think the regmap lock is opt-out, so I don't think we need to set an > > custom lock callback for the regmaps in this driver. > > > > Jonathan, do read_raw() and write_raw() require explicit locking? > > The don't provide their own locking. Depending on the access pattern the > underlying bus locking may be sufficient. If you have read modify write > cycles though you'll want locking at the appropriate level for that > which might well be at the level of regmap. > > Jonathan If read_raw() can be called concurrently multiple times then we risk changing the ADC channel while the analog-to-digital conversion is in progress, thus resulting in an incorrect reported value. Looks like we'll need an explicit lock for this after all, so I'll create a precursor patch addressing that. William Breathitt Gray
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