> -----Original Message-----
> From: William Breathitt Gray <william.gray@xxxxxxxxxx>
> Sent: 01 October 2022 18:44
> To: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Cc: William Breathitt Gray <wbg@xxxxxxxxxx>; Rob Herring
> <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@xxxxxxxxxx>; Philipp Zabel
> <p.zabel@xxxxxxxxxxxxxx>; Michael Turquette <mturquette@xxxxxxxxxxxx>;
> Stephen Boyd <sboyd@xxxxxxxxxx>; Geert Uytterhoeven
> <geert+renesas@xxxxxxxxx>; Lee Jones <lee@xxxxxxxxxx>; Uwe Kleine-
> König <u.kleine-koenig@xxxxxxxxxxxxxx>; linux-pwm@xxxxxxxxxxxxxxx;
> linux-iio@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; Chris Paterson
> <Chris.Paterson2@xxxxxxxxxxx>; Biju Das <biju.das@xxxxxxxxxxxxxx>;
> Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>;
> linux-renesas-soc@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH RFC 0/8] Add RZ/G2L MTU3a MFD and Counter driver
>
> On Sat, Oct 01, 2022 at 05:12:56PM +0000, Biju Das wrote:
> > > > > You can then control the phase selection using a top-level
> > > > > Counter device extension (e.g.
> > > > > /sys/bus/counter/devices/counter0/phase)
> > > that
> > > > > configures whether you're in 16-bit phase or 32-phase counting
> > > mode.
> > > >
> > > > So I need to introduce a new sysfs called phase. Use that one
> for
> > > > Selecting the external clock pin for phase counting mode.
> > > > Please correct me if I am wrong??
> > > >
> > > > Hardware supports 4 pins for phase counting mode,
> > > >
> > > > MTCLKA Input External clock A input pin (MTU1/MTU2 phase
> counting
> > > mode
> > > > A phase input) MTCLKB Input External clock B input pin
> (MTU1/MTU2
> > > > phase counting mode B phase input) MTCLKC Input External clock C
> > > input
> > > > pin (MTU2 phase counting mode A phase input) MTCLKD Input
> External
> > > > clock D input pin (MTU2 phase counting mode B phase input)
> > > >
> > > > For MTU1, it is fixed MTCLKA and MTCLKB.
> > > > But for MTU2, it can be either 0-{ MTCLKA, MTCLKB} or 1 - {
> MTCLKC
> > > > , MTCLKD} On reset it is set to { MTCLKC , MTCLKD}.
> > > >
> > > > Cheers,
> > > > Biju
> > >
> > > It doesn't need to be named "phase" specifically, but it seems
> like
> > > a new sysfs file will be necessary in order to select the proper
> > > phase counting mode.
> > >
> > > Are these MTCLK signals the quadrature A and B Signals you defined
> > > in the counter driver?
> >
> > Yes, that is correct.
> >
> > Cheers,
> > Biju
>
> You should define a Signal then for each of the four MTCLK inputs.
> Create synapse arrays for each Count respectively; e.g. Count 0 will
> have Synapses for MTCLKA and MTCLKB, but Count 1 will probably need
> Synapses for all four Signals (the action mode for two of them will be
> COUNTER_SYNAPSE_ACTION_NONE depending on the configuration set).
OK.
>
> What is the configuration when 32-bit phase counting mode is selected?
LWA Bit (MTU1/MTU2 Combination Longword Access Control) needs to set for 32-bit phase counting mode.
b0 LWA 0 R/W MTU1/MTU2 Combination Longword Access Control
0: 16-bit access is enabled.
1: 32-bit access is enabled.
> Does MTCLKA and MTCLKB serve as the counting signals in this case,
For 16-bit and 32-bit counting signals same. We can set
1) MTU 1 and MTU2 signals as MTCLKA and MTCLKB
Or
2) MTU 1 signal as MTCLKA and MTCLKB and MTU2 signals as MTCLKC and MTCLKD
b1 PHCKSEL 1 R/W External Input Phase Clock Select
Selects the external clock pin for phase counting mode.
0: MTCLKA and MTCLKB are selected for the external phase clock.
1: MTCLKC and MTCLKD are selected for the external phase clock
> with overflows on the MTU1 register incrementing the MTU2 register?
No. that won't happen as we need to use different register for Long word access
These are the regiters used
16-bit:- TCNT{MTU1,MTU2}, TGRA{MTU1,MTU2}, and TGRB{MTU1,MTU2},
32-bit:- MTU1.TCNT_1_LW, MTU1.TGRA_1_LW and MTU1.TGRB_1_LW
Counter in MTU1 MTU1.TCNT Word MTU1.TCNT_1_LW Longword
Counter in MTU2 MTU2.TCNT Word
General register A in MTU1 MTU1.TGRA Word MTU1.TGRA_1_LW Longword
General register A in MTU2 MTU2.TGRA Word
General register B in MTU1 MTU1.TGRB Word MTU1.TGRB_1_LW Longword
General register B in MTU2 MTU2.TGRB Word
Cheers,
Biju
