From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
---
drivers/staging/iio/frequency/ad9832.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/frequency/ad9832.c
index f43464db618a..ce9fcba6bc5c 100644
--- a/drivers/staging/iio/frequency/ad9832.c
+++ b/drivers/staging/iio/frequency/ad9832.c
@@ -112,7 +112,7 @@ struct ad9832_state {
* transfer buffers to live in their own cache lines.
*/
union {
- __be16 freq_data[4]____cacheline_aligned;
+ __be16 freq_data[4] __aligned(IIO_DMA_MINALIGN);
__be16 phase_data[2];
__be16 data;
};
--
2.37.1
