Rob, Clk experts, questions for you below. Jonathan On Thu, 13 Dec 2018 17:39:22 -0800 Stephen Boyd <sboyd@xxxxxxxxxx> wrote: > Quoting Jonathan Cameron (2018-12-08 07:29:54) > > On Thu, 6 Dec 2018 11:10:51 +0200 > > Mircea Caprioru <mircea.caprioru@xxxxxxxxxx> wrote: > > > > > This patch adds a clock to the state structure of ad7192 for getting the > > > external clock frequency. This modifications is in accordance with clock > > > framework dt bindings documentation. > > > > > > Signed-off-by: Mircea Caprioru <mircea.caprioru@xxxxxxxxxx> > > > > +cc Rob and the clk list for advise on how to do the binding for this one. > > > > It is basically 2 pins, you can put a clock in on one of them or connect > > a crystal across them. The driver has to set a register to say which is > > the case. > > > > Current proposal is two optional clocks (fall back to internal oscillator) > > but that doesn't seem to be commonly done, so I'm wondering if there > > is a 'standard' way to handle this sort of thing. > > > > I'm not sure I fully understand, but I think perhaps > assigned-clock-parents would work? Or does that not work because either > way some parent is assigned, either the crystal or the optional clk that > isn't a crystal? > My concern is they aren't really separate clock inputs. They are just different ways of providing the same fundamental clock. So I think we may want to just provide a single clock and have another dt binding to say what it is. So lots of ways we could do it, but I'm not sure what the right one to go with is! Jonathan
